Controller Area Network with Flexible Data-Rate (FDCAN)¶
lbuild module: modm:platform:can
This module is only available for stm32{c0,g0,g4,h5,h7,l5,u3,u5}.
Instance Options¶
These options are available for each instance of this module.
buffer.rx¶
Default: 32
Inputs: [0 .. 32 .. 64Ki-2]
buffer.tx¶
Default: 32
Inputs: [0 .. 32 .. 64Ki-2]
message_ram.extended_filter_count¶
This option is only available for stm32h7.
Default: 8
Inputs: [1 .. 8 .. 64]
message_ram.rx_fifo_0_elements¶
This option is only available for stm32h7.
Default: 14
Inputs: [1 .. 14 .. 64]
message_ram.rx_fifo_1_elements¶
This option is only available for stm32h7.
Default: 14
Inputs: [1 .. 14 .. 64]
message_ram.standard_filter_count¶
This option is only available for stm32h7.
Default: 28
Inputs: [1 .. 28 .. 128]
message_ram.tx_fifo_elements¶
This option is only available for stm32h7.
Default: 14
Inputs: [1 .. 14 .. 32]
tx_hw_queue_mode¶
Controls the order in which frames are popped from the hardware TX queue (see message_ram.tx_fifo_elements). Does not affect the optional software buffer (buffer.tx), which is always popped in FIFO order.
FIFO: transmit frames in the order they were enqueued. Priority: transmit the frame with the lowest arbitration ID first.
Default: FIFO
Inputs: [FIFO, Priority]
Dependencies¶
Limited availability: Check with 'lbuild discover' if this module is available for your target!